Feature selection can improve the performance of data classification effectively. In order to further improve the solving ability of Ant Colony Optimization (ACO) on feature selection, a hybrid Ant colony optimization with Brain storm Optimization (ABO) algorithm was proposed. In the algorithm, the information communication archive was used to maintain the historical better solutions, and a longest time first method based on relaxation factor was adopted to update archive dynamically. When the global optimal solution of ACO was not updated for several times, a route-idea transformation operator based on Fuch chaotic map was used to transform the route solutions in the archive to the idea solutions. With the obtained solutions as initial population, the Brain Storm Optimization (BSO) was adopted to search for better solutions in wider space. On six typical binary datasets, experiments were conducted to analyze the sensibility of parameters of the proposed algorithm, and the algorithm was compared to three typical evolutionary algorithms:Hybrid Firefly and Particle Swarm Optimization (HFPSO) algorithm, Particle Swarm Optimization and Gravitational Search Algorithm (PSOGSA) and Genetic Algorithm (GA). Experimental results show that compared with the comparison algorithms, the proposed algorithm can improve the classification accuracy by at least 2.88% to 5.35%, and the F1-measure by at least 0.02 to 0.05, which verify the effectiveness and superiority of the proposed algorithm.
Aiming at the problem that the scale of integrated circuits and the number of on-chip registers are increasing, which makes the verification more difficult, a lightweight register model was proposed. Firstly, a concise underlying structure was designed, and parameterized settings were combined to reduce the memory consumption of the register model at runtime. Then the register verification requirements at different levels such as module level and system level were analyzed, and SystemVerilog language was used to implement various functions required for verification. Finally, the built-in test cases and register model automatic generation tools were developed to reduce the setup time of the verification environment in which the register model was located. The experimental results show that the proposed register model is 21.65% of the Universal Verification Methodology (UVM) register model in term of memory consumption at runtime; in term of function, the proposed register model can be applied to traditional UVM verification environments and non-UVM verification environments, and the functions such as read-write property, reset value and backdoor access path of 25 types of registers are checked. This lightweight register model has good universality and flexibility in engineering practice, meets the needs of register verification, and can effectively improve the efficiency of register verification.